A programmable logic controller (PLC) is a module for counting a high-speed pulse train such as signals from a pulse generator or an encoder which cannot be processed with a typical counter command.
In general, to operate the PLC high speed counter, a mode for the PLC high speed counter is established using a device such as a PC or HMI. In this case, the PLC high speed counter operates in the linear counter mode or ring counter mode depending on the established mode.
In the established mode, the PLC high speed counter counts a high-speed pulse train input from the encoder and then stores the current value.
When the PLC high speed counter is in the ring counter mode, the PLC high speed counter counts the pulse train such that the count value is between a minimum ring count value and the maximum ring count value, which are set by the user, and then stores the current value.
When the PLC high speed counter is in the linear counter mode, the PLC high speed counter counts the pulse train such that the count value is within a count range, and then stores the current value.
A PC or an HMI reads the current value from the PLC high speed counter and displays the same on the screen to inform the user of the present count value (a currently counted value).
FIG. 1 illustrates a process of counting a current value according to a counter mode of the PLC high speed counter when the maximum count range is signed 32 bits.
(a) in the FIG. 1 illustrates a process of counting a current value in the linear counter mode of the PLC high speed counter.
When a pulse train is input to the PLC high speed counter, the PLC high speed counter adds a current value according to an addition condition. Once the current value reaches the upper limit (2,147,483,647) of the count range, the PLC high speed counter does not perform addition anymore even if an addition condition is triggered.
On the other hand, once the current value reaches the lower limit (−2,147,483,647) of the count range after the PLC high speed counter subtracts current values according to a subtraction condition, the PLC high speed counter does not perform subtraction anymore even if a subtraction condition is triggered.
(b) in the FIG. 1 illustrates a process of counting a current value in the ring counter mode of the PLC high speed counter. When the PLC high speed counter operates in the ring counter mode, the user sets the maximum ring count value and the minimum ring count value.
When a pulse train is input to the PLC high speed counter, the PLC high speed counter adds or subtracts a current value according to the addition condition or subtraction condition.
In this case, at the moment the current value reaches the maximum ring count value after the PLC high speed counter adds current values, a Carry is triggered and the current value is changed to the minimum ring count value. Thereafter, the PLC high speed counter performs addition when an addition condition is triggered.
On the other hand, at the moment a current value reaches the minimum ring count value after the PLC high speed counter subtracts current values, a Borrow is triggered and the current value is changed to the maximum ring count value. Thereafter, the PLC high speed counter performs subtraction when a subtraction condition is triggered.
FIG. 2 is a flowchart illustrating count processing of a PLC high speed counter according to the conventional art.
When a pulse train is input to the PLC high speed counter, the PLC high speed counter pauses a PLC scan program, generates an interrupt and performs a count process routine every time the PLC high speed counter senses a rising edge and a falling edge.
In this case, as shown in FIG. 2, the PLC high speed counter determines whether the counter mode is the linear counter mode or the ring counter mode in the interrupt routine every time a pulse train is input. Thereby, the PLC high speed counter performs branching to implement addition, subtraction or ring count.
Accordingly, in conventional cases, a high speed counter function needs to be performed after an interrupt is triggered at each edge of an input pulse train, and a complex branching process should be performed according to the count mode as shown in FIG. 2. Thereby, a long time is taken to process interrupts.
Thereby, when a high-speed pulse train is input, resources of the MPU of the PLC high speed counter are excessively occupied to process interrupts and accordingly the processing speed of the PLC scan program is lowered.
In addition, when a pulse train is input through multiple high speed counter channels simultaneously, an input pulse may fail to be counted.
Furthermore, branching of the process routine is necessary for respective counts, and therefore software capacity increases, a long time is taken to perform writing, and the software is difficult to be maintained.